1. Field of the Invention
The present invention generally relates to a memory system, and in particular, to a system and method for providing concurrent row and column commands in a memory system using separate device selection mechanisms.
2. Related Art
A typical memory system includes a memory controller and memory devices, such as dynamic random access memory (DRAM) devices, coupled thereto. In some systems, a processor performs memory controller functions. As used herein, the term memory controller includes such a processor. The memory devices are usually placed on memory modules, and the modules are connected to the memory controller through a memory interface. The memory interface provides communication between the memory controller and the memory devices. For example, the memory interface may contain chip select lines, address bus lines, command signal lines, and data bus lines.
Increasing demand for higher computer performance and capacity has resulted in a demand for faster and more efficient memory systems. When instructions from a central processing unit (CPU) of a computer are carried out, information and data are constantly transmitted from the memory controller to the memory devices, and vice versa. Intense read and write traffic in a memory system often results when the computer is under a heavy workload and simultaneously running several applications. Because data is constantly moving between the memory controller and the memory device, one way to increase the efficiency of a memory system is to improve data bandwidth in the data bus lines and command bandwidth in the command signal lines. The data bandwidth and command bandwidth can be thought of as the amount of data and command being sent from the memory controller to the memory device, or from the memory device to the memory controller, at a given time, respectively.
Even though some prior art memory systems, such as a Double Data Rate-Synchronous DRAM (DDR) system, have a peak data bandwidth of about 1.6 gigabytes per second, these prior memory systems typically achieve only about 65% efficiency on most computer applications. This is partly the result of the memory controller having to spend time waiting for the memory devices to be ready for an operation before the memory controller can issue another command. For example, before a DDR system can do a read operation, the portion of the memory devices containing the data to be read must be pre-charged and activated. After pre-charging and activating the applicable portion, there is a timing constraint in which the DDR system must wait before the next operation on the portion can be initiated. This timing constraint is commonly known as tRCD, which stands for Row to Column Decode time or delay.
FIG. 1 shows an illustrative example of a timing diagram of a prior art DDR system. In this example, the DDR system desires to read from two separate sub-arrays in a memory device. The top signal in the timing diagram represents a single chip select signal 10 to that memory device. The bottom signal in the timing diagram represents command signals 20 issued from the memory controller. While the chip select signal 10 is low, the memory device is selected by the memory controller to perform the applicable commands. Here, the memory controller sends out a first read command 22 to read data from a first sub-array of the memory device, a pre-charge command 23 and an activate command 24 to pre-charge and activate a second sub-array of the memory device, and a read command 28 to read data from a second sub-array of the memory device. The timing of commands shown are illustrative in nature since the clock counts of the timing relationships depend on a number of factors, including speed grade of the device, frequency of operation, amount of memory populated. Because of intrinsic limitations in the DDR memory system, the read and pre-charge commands 22, 23 can only be performed sequentially. The length of a timing block 26 represents the timing constraint tRCD that the system must wait before the second read command 28 to the second sub-array can be initiated. Because the DDR system has to carry out these commands sequentially and wait for the tRCD to elapse before the second command can be initiated, data bus lines between the memory devices and the memory controller remain empty between transmitting data read from the first read command and transmitting data read from the second read command. The data bus lines are unused during the pre-charge period, the activate period and the tRCD timing constraint. As the result, the data bus lines are not efficiently used, and data bandwidth suffers.
In other memory systems, such as a Rambus DRAM (RDRAM) system, solutions have evolved to increase the efficiency of data bandwidth. In the RDRAM system, instead of sending a command from a memory controller to a memory device in one clock, the commands are organized in a packet format. The command packet is sent to memory devices in multiple clocks, usually in eight clock edges, with each clock edge being used to send a portion of the packet. The command packet, with its large size, is able to encode information that allows row and column commands to be carried out concurrently, as opposed to sequentially as in a DDR system. For example, pre-charge or activate is a row command, and read is a column command. This improves command bandwidth and allows data bandwidth to be used more efficiently. However, because multiple clocks are needed to transmit the packet, certain delay is introduced. For example, in a 400-megahertz system, eight clock edges would require 10 nanoseconds to send the command packet. Therefore, there is a need for a system and method to provide concurrent row and column commands that would improve data bandwidth but would not introduce delay.